AI infrastructure continues to evolve to support larger models, growing datasets and increasingly memory-intensive workloads. As these demands grow, memory capacity, bandwidth, utilization and scalability are becoming critical considerations for the next generation of AI systems.
At AI Infra Summit 2026, taking place September 15–17, 2026, in Santa Clara, California, the CXL Consortium will highlight how CXL technology can help the industry address these challenges by enabling new approaches to memory expansion, sharing and system architecture.
Visit the CXL Pavilion – Booth 213
Stop by the CXL Pavilion at Booth 213 to explore CXL solutions and demonstrations from Consortium members Liqid, Primemas and VIAVI.
The demonstrations will showcase different aspects of the growing CXL ecosystem and how CXL can help address memory and infrastructure challenges for AI and other data-intensive workloads.
Liqid | Software-Defined Memory and GPU Pooling Infrastructure
Compute, storage, and networking all became poolable resources. Memory did not. It stayed locked in the server with the CPU socket, sized at purchase, and stranded there for the life of the server. Liqid delivers a shared-memory system architecture for AI and HPC with up to 160TB of DDR5 as an addressable pool that one or more hosts in the rack can claim, share, or release without rebooting or recabling. It is ideal for KV Cache offload, long-context inference, vector and graph indexes for retrieval, and intermediate data in AI-assisted simulation, all of which grow faster than HBM capacity or per-socket DIMM slots.
During the event, Liqid will show a fully disaggregated, software-defined memory pooling solution. In a Liqid rack-scale configuration, up to 160TB of DRAM can be dedicated to a single host or dynamically allocated and shared across up to 16 server nodes. Real-time allocation of terabytes of memory enables zero stranded capacity and massive performance scaling when needed. Learn more by visiting www.liqid.com.
Primemas | PMA16 CXL AIC in a JBOM Memory Expansion System: Rack-Scale Memory for AI Infrastructure
AI inference, RAG, and vector-pipeline workloads are increasingly memory-bound rather than compute-bound. PMA16’s CXL Type-3 expansion, enterprise RAS (Chipkill, E2E protection), and security features (link-level encryption, attestation) show a production-ready way to scale memory independently of CPU/GPU count in AI server racks. The PMA16 is a PCIe Gen5, CXL Type-3 AIC with 16 DDR5 RDIMM slots, delivering up to 4TB (256GB RDIMMs) or 8TB (512GB RDIMMs) via the Falcon-1 controller over dual CXL 3.2 links at 64GB/s. This demo shows PMA16 cards serving as the building block for a JBOM-class, rack-scale memory system that pools memory beyond local DRAM limits. Visit https://www.primemas.com/ to learn more.
VIAVI | Powering AI Infrastructure: CXL 3.2 link between VIAVI CXL RC Exerciser and Montage CXL Retimer and Controller
VIAVI will showcase a live demo using a VIAVI exerciser/root complex connected through a Montage Technology PCIe Gen6 retimer to a Montage Technology CXL 3.2 controller endpoint. The setup will highlight low-latency retimer performance and CXL 3.2 clock-mode latency, while showing how VIAVI tools can validate the complete link. CXL enables more flexible and scalable memory architecture for AI infrastructure. This live VIAVI + Montage Technology demo shows a CXL 3.2 link through a PCIe Gen6 retimer, highlighting low-latency performance and how to test and validate the complete link.
Together, these demonstrations will provide attendees an opportunity to see how the CXL ecosystem is advancing from specification to real-world solutions across hardware, software, infrastructure, and test and validation. Learn more by visiting https://www.viavisolutions.com/en-us/products/pcie-60.
Hear From CXL Experts at the Demo Theater
In addition to demonstrations at the CXL Pavilion, attendees can hear directly from CXL Consortium members on how CXL is addressing the growing memory requirements of AI infrastructure.
- Title: Boost your AI performance with CXL
- Date and time: Wednesday, September 16 | 12:45 – 1:30 pm PT
- Location: Expo Theater 1
- Moderator: Siamak Tavallaei (CXL Board Director / Samsung)
- Panelists: Sandeep Dattaprasad (Astera Labs), Hasan Maruf (Meta), Joseph Baco (Primemas)
Exploring the AI Memory Wall
Dr. Debendra Das Sharma, CXL Consortium Board Chair, will also moderate the “Scaling the AI Memory Wall – Where Model Architecture Meets Hardware” panel on Wednesday, September 16, from 4:10–4:50 pm PT.
Attend the discussion to explore developments in memory technology, architecture, and system design and how they can improve the performance, efficiency, and scalability of AI workloads. Topics will range from HBM roadmaps to emerging approaches to memory management and the technologies needed to support the next generation of AI infrastructure.
Join the CXL Consortium at the AI Infra Summit to see CXL technology in action, hear from industry experts, and learn how an open industry standard can help enable scalable, efficient AI infrastructure. Attendees can use code CXLCONSORTIUM15 to receive 15% off a full-access ticket. Register to attend the event HERE.
We hope to see you in Santa Clara!