Compute Express Link® (CXL®) is an industry-supported Cache-Coherent Interconnect for Processors, Memory Expansion and Accelerators. CXL technology maintains memory coherency between the CPU memory space and memory on attached devices, which allows resource sharing for higher performance, reduced software stack complexity, and lower overall system cost. This permits users to simply focus on target workloads as opposed to the redundant memory management hardware in their accelerators.
CXL is designed to be an industry open standard interface for high-speed communications, as accelerators are increasingly used to complement CPUs in support of emerging applications such as Artificial Intelligence and Machine Learning.
CXL 3.1 Specification is Available Now
The CXL 3.1 specification builds on previous iterations to optimize resource utilization, create trusted compute environments as needed, extend memory sharing and pooling to avoid stranded memory, and facilitate memory sharing between accelerators.
Key Highlights of the CXL 3.1 Specification:
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CXL Fabric improvements and extensions
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Fabric Decode/Routing requirements
- Fabric Manager API definition for PBR (Port Based Routing) Switch
- Host-to-host communication with Global Integrated Memory (GIM) concept
- Direct P2P CXL.mem support through PBR Switches
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- Trusted-Execution-Environment Security Protocol (TSP)
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Memory expander improvements
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Extended Meta Data with support for up to 32-bits per cache line of host specific state
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Improved visibility into CXL memory device errors
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Expanded visibility and control over CXL memory device RAS (Reliability, Availability, Serviceability)
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Full backward compatibility with CXL 2.0, CXL 1.1, and CXL 1.0
Download the CXL 3.1 white paper for more details.