Compute Express Link® (CXL®) is an industry-supported Cache-Coherent Interconnect for Processors, Memory Expansion and Accelerators. CXL technology maintains memory coherency between the CPU memory space and memory on attached devices, which allows resource sharing for higher performance, reduced software stack complexity, and lower overall system cost. This permits users to simply focus on target workloads as opposed to the redundant memory management hardware in their accelerators.
CXL is designed to be an industry open standard interface for high-speed communications, as accelerators are increasingly used to complement CPUs in support of emerging applications such as Artificial Intelligence and Machine Learning.
CXL 4.0 Specification is Available Now
The CXL 4.0 doubles bandwidth from 64GTs to 128GTs, adds support for bundled ports, and enhances memory RAS features.
Key features of the CXL 4.0 specification
- Doubles the bandwidth to 128GTs with zero added latency
- Enables rapid data movement between CXL devices, directly improving system performance
- Maintains previously enabled CXL 3.x protocol enhancements with the 256B Flit format
- Introduces the concept of native x2 width to support increased fan-out in the platform
- Support for up to four retimers for increased channel reach
- Implements CXL bundled port capabilities
- Ability to combine device ports between Host and CXL accelerators (Type 1/2 devices) to increase bandwidth of the connection
- Delivers memory RAS enhancements
- Improves reliability, error visibility, and maintenance efficiency
- Continued full backward compatibility with CXL 3.x, 2.0, 1.1, and 1.0