Compute Express Link® (CXL®) is an industry-supported Cache-Coherent Interconnect for Processors, Memory Expansion and Accelerators. CXL technology maintains memory coherency between the CPU memory space and memory on attached devices, which allows resource sharing for higher performance, reduced software stack complexity, and lower overall system cost. This permits users to simply focus on target workloads as opposed to the redundant memory management hardware in their accelerators.
CXL is designed to be an industry open standard interface for high-speed communications, as accelerators are increasingly used to complement CPUs in support of emerging applications such as Artificial Intelligence and Machine Learning.
CXL 3.2 Specification is Available Now
The CXL 3.2 Specification optimizes CXL Memory Device monitoring and management, enhances functionality of CXL Memory Devices for OS and Applications, and extends security with the Trusted Security Protocol (TSP).
Highlights of the CXL 3.2 Specification:
- Optimized CXL Memory Device monitoring and management
- New CXL Hot-Page Monitoring Unit (CHMU) for memory tiering
- Common event record
- Compatibility with PCIe Management Message Pass Through (MMPT)
- CXL online firmware (FW) activation capabilities
- Enhanced functionality of CXL Memory Devices for OS and Application
- Post Package Repair (PPR) enhancements
- Additional performance monitoring events for CXL Memory Devices
- Extends security with the Trusted Security Protocol (TSP)
- New Meta-bits Storage Feature for Host-only Coherent Host-Managed Device Memory (HDM-H) address regions
- Improved security by expanding IDE protection
- Increases security of Host-only Coherent Device-Managed Memory with Back-Invalidation (HDM-DB) memory devices
- Enhances compliance tests for interoperability
- Full backward compatibility with all previous CXL specifications