The CXL Consortium hosted a webinar exploring the benefits of CXL memory sharing and how CXL shared memory can improve performance for Big Data Analytics, AI, and more. During the webinar, CXL Consortium members Astera Labs, Micron Technology, UnfabriX, and XConn Technologies also shared how they are deploying CXL memory sharing to improve performance for finance, AI, and database applications.
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We received great questions from the audience during the live Q&A but were not able to address them all during the webinar. Below, we’ve included answers to the questions that we didn’t get to during the live webinar.
Q: For FamFS, can clients write the file system in the future? What are the obstacles to achieve this capability?
Micron: The biggest challenge is the lack of hardware-based cache coherency support. Without the support, two different hosts could update an object in shared memory simultaneously. That said, we have a few ideas to add support for clients to make updates to the filesystem.
Q: If XConn Technologies’ CXL Switch 2.0 is in the production line now, when can we expect the CXL 3.0 Port Based Routing Switch?
Xconn Technologies: The CXL 3.X switch supporting Port Based Routing (PBR) should be available in 2026 or later.
Q: When do you anticipate systems supporting hardware coherency over CXL becoming available? Are there active efforts underway in this area? What are the current limitations, and how might we overcome them?
UnifabriX: CPU vendors are planning to support hardware coherence, but the timeline is to be determined. Currently, the CXL protocol offers a broad range of tools to enable coherence with great performance and low latency. Additionally, there are systems available from a few vendors, including UnifabriX MAX-Memory, that are ready for testing today.
Q: If you are using max memory for CXL memory sharing, what is the access latency if we want to access the same object cache-coherently?
UnifabriX: MAX-Memory offers multiple CXL connections to multiple hosts with link aggregation capability to enhance bandwidth (per node). Each host will appear as a multi-socket system, e.g. 4/8 socket server / NUMA nodes (based on configuration), and latency will be the same as a multi-socket server.
Q: How will Nvidia NVLink benefit CXL memory?
Astera Labs: NVLink enables communication between Nvidia accelerators and as such it is orthogonal to what CXL memory is meant to do. However, if we think of benefits of CXL memory towards accelerator applications (Nvidia or other accelerators), what we can say is that inference and training applications have memory bottleneck, and rely on CPU attached high latency storage. CXL memory can improve the performance and add significant memory capacity for such applications.
Q: Are the CMMs shared/pooled among the servers? What is the physical mechanism to achieve sharing/pooling?
Micron: The CXL Memory Modules are shared across the servers. CXL switches are required to achieve memory sharing and pooling.
Q: Will coherency become a bottleneck for multi-host?
Astera Labs: No, CXL has features to ensure coherency in a multi-host environment. For example, the CXL 3.0 specification enables a back-invalidate feature, allowing hosts to invalidate cache lines. The protocol also includes metadata bits that can be used to indicate the state of the cache, ensuring coherency in a multi-host environment.