Join the CXL Consortium at the Future of Memory and Storage (FMS) 2024 Event

Compute Express Link® (CXL®) is a cache-coherent interface that enables memory expansion and heterogeneous memory for disaggregated systems. CXL technology helps reduce storage latency, boost system performance and efficiency, and break through the limitations of current memory interface technology. This panel will share data points from CXL technology implementations to show how CXL meets the memory capacity and bandwidth needs for AI, HPC, and in-memory database applications. Attendees will gain insights into the solutions that are readily available within the market.

This session discusses how memory innovations are leveraging technologies like persistent memory, memory tiering, and the latest addition of CXL. Open-source fabric management and orchestration layers for CXL devices and switches can offer best practices for seamless integration with familiar platform management tools. Additionally, with CXL 1.1, servers now supporting memory expansion through CXL Memory Add-in Cards and E3.S memory modules, sellers and buyers can now integrate cost-effective and high-capacity solutions. Attendees will gain valuable insights into the benefits and strategies of incorporating mixed memory configurations in server environments, ultimately optimizing application performance.

Astera Labs: Importance of Pre-boot Environment for CXL Type 3 Devices
Data-intensive workloads in the modern AI landscape necessitate memory solutions with larger capacities and higher bandwidths. CXL Type 3 memory expansion (CXL.mem) can help overcome existing systems challenges by adding memory bandwidth and capacity beyond available native attached memory on DIMM slots. These CXL Type 3 based platforms rely on system software enumeration before Operating System (OS) loads for device discovery. This presentation will shed light on the importance of properly configuring and running tests on CXL Type 3 devices in a pre-boot environment to ensure reliable operation of the platform in a data center.

Attendees will learn about pre-boot environment aspects such as CXL topology discovery, memory configuration, performance characteristics of the attached components, as well as necessary system level tests for Type 3 devices.

Montage Technologies: CXL 2.0 Use Case – Using both DDR4 and DDR5 on the same server to allow memory and bandwidth scaling
Montage Technology is the leading CXL controller supplier in the industry, with design wins from all the key suppliers. Montage will be presenting its CXL 2.x MXC controller, featuring industry-leading latency and bandwidth. The presentation will demonstrate, on Intel and AMD’s latest servers, the ability to simultaneously run DDR4 and DDR5 memory modules using a CXL Add-In Card. Additionally, it will showcase the enhancement of bandwidth and capacity through the use of CXL E3 DDR5 modules from SK and Samsung.

Xconn Technologies: CXL 2.0 Fabric Deployment for a Composable Memory System
Composable Memory System (CMS)is an emerging paradigm that facilitates dynamic and unified memory management across diverse memory technologies, interconnects, and hierarchies. This approach addresses the complex demands of memory performance, capacity, latency, throughput, data sharing, and scalability by emerging applications.

CXL 2.0 proposes a switch fabric for multiple hosts with the capability of dynamically sharing a CXL memory pooled resource. With a switch fabric, it can increase the memory pooled capacity to another scale in this CMS infrastructure.

Basing on the availability of CXL 2.0 host, CXL 2.0 switch and CXL 2.0 device in the market, we can deploy this composable memory system in data centers. We would like to share our experiences in this memory pooled infrastructure with CXL 2.0 fabric technology.

As CXL integration expands into large systems, the focus shifts to bringing CXL to embedded environments like motherboards. We’ll discuss how next-gen systems are using CXL’s versatile interfaces for memory, storage, and accelerators. The session will also discuss the latest options for CXL memory expansion in X86 servers, both volatile and non-volatile, with a glimpse into future trends and optical connectivity advancements, with real-world examples. We will also take a look at the impact of optical CXL on datacenter architecture for AI and LLM processing, offering bandwidth and latency solutions for massive memory pooling applications.

In the quest to reduce memory costs in server/datacenter operations, pooling and sharing of memory have emerged as viable solutions. By utilizing mechanisms like MH-SLD and MLD provided by CXL 3.1, organizations can optimize memory utilization and minimize data movement expenses. This session will examine the benefits of MH-SLD over MLD for initial CXL device deployment, particularly focusing on the efficiency of dynamic memory allocation using DCD features. Additionally, a detailed look at the implementation of a CXL memory pooling system and its performance study will be showcased, revealing insights on memory expansion, pooling, and sharing within a multi-host environment.

In this session, we dive into the fiery world of hot data detection for CXL memory, emphasizing the importance of understanding data placement in heterogeneous memory for optimal application performance. We discuss the significance of data and control plane separation in CXL memory, highlighting its load/store access capabilities and command-based interface for RAS features. Additionally, we examine memory compression within CXL memory controllers, and touch on use cases for CXL-based active memory tiering and near memory accelerators, shedding light on the challenges and expected performance metrics in implementing these innovative approaches.

The exciting world of CXL continues to evolve, with advancements in GenZ, CCIX, and OpenCAPI being incorporated into CXL specifications. But where is this technology headed? This session will provide valuable insights on the practical applications of CXL, from its core purpose to the needs of potential users, culminating in a forecast of CXL adoption and its impact on future computing architectures. We will also explore the potential of CXL in memory expansion and flash memory applications, offering cost-effective solutions for scaling memory capacity and enhancing performance in AI use cases.

In the world of AI and data systems, the key to unlocking peak performance lies not in sheer computational power, but in the balance of memory capacity and bandwidth. The advent of Compute Express Link (CXL) technology offers a groundbreaking solution to this challenge, ushering in a new era of data-centric computing. With CXL, data center infrastructure can be optimized for maximum efficiency, reducing the strain on processor complexes and networks. The benefits are clear: improved performance, resource utilization, and power efficiencies, ultimately leading to lower operating costs. This session will delve into the transformative potential of CXL technology and its ability to revolutionize memory and computing in AI and data systems.