AI infrastructure, in-memory databases, and HPC workloads continue to drive requirements for memory capacity, performance, and data resilience. At the CXL Pavilion at SC26 in Chicago, IL, Netlist will demonstrate three CXL memory proof-of-concept (POC) designs showing complementary approaches to intelligent memory tiering, data persistence, and memory expansion and reuse. SC26 runs November 15–20, 2026; the exhibit hall gala is November 16, and regular exhibits run November 17–19.
Target applications across the portfolio include AI infrastructure and KV-cache management, in-memory databases (IMDB), virtual machines (VMs), HPC, and other memory-intensive workloads. Together, the demos show how CXL can manage data across memory tiers, preserve critical data, and extend the life of existing memory assets.
NVvault™-HM
NVvault™-HM is a POC design for intelligent memory tiering that combines DRAM and NAND for high-capacity CXL memory expansion. The architecture uses DRAM as a high-speed cache for NAND-backed capacity, helping manage hot, warm, and cold data through tiering, telemetry, and data migration.
The design targets AI infrastructure and KV-cache management, databases, analytics, and other capacity-intensive workloads.
NVvault™-PM
NVvault™-PM is a CXL-attached non-volatile memory POC designed to combine DRAM-class performance with data persistence. Built on CXL Type 3 over PCIe Gen5, the architecture pairs low-latency DRAM with onboard NAND backup and an embedded energy source to protect DRAM-resident data during power loss.
The design targets persistent, cache-coherent memory expansion for applications such as KV-cache management, AI/ML checkpointing, and accelerated recovery in database and HPC environments.
NVvault™-D4
NVvault™-D4 is a CXL-attached DDR4 memory expansion POC designed to extend the value of existing DDR4 memory assets. The architecture makes DDR4 available as expanded host memory, increasing memory capacity and enabling DDR4 reuse.
The design targets in-memory databases, virtual machines, HPC, and other enterprise workloads.
CXL Pavilion at SC26
Together, the three POC designs illustrate how CXL can support memory tiering, persistent memory and DDR4 reuse. Each approach targets a different combination of capacity, performance, data persistence, and memory efficiency.
Visit the CXL Pavilion at SC26 (Booth no. 1218) to see how CXL-attached memory can support intelligent tiering across DRAM and NAND, protect DRAM-resident data through power loss, and extend the use of existing DDR4 memory.