Datacenter resources are increasingly strained by the escalation of high-performance computational workloads. Datacenters require heterogeneous processing and memory systems to support numerous applications, including servers, networking, storage, visual computing, edge infrastructure, and artificial intelligence. Rapid developments in computing infrastructure requirements are driving the need for a new interface that meets the increasing demands for high data throughput, coherency and low latency. CXL®, a relatively new standard backed by all the major CPU vendors, enables cache coherence and memory pooling and sharing, allowing the sharing of memory between devices and preventing large dataset copying during analysis. It achieves this with a new protocol stack that also delivers very low latency.
The evolution of the CXL standard has enabled increasing functionality that moves us closer and closer to a disaggregated and composable systems for HPC applications, while maintaining backward compatibility with previous CXL specification revisions.
CXL 1.1 enables point-to-point connections between a host and a device and supports dynamic multiplexing between three protocols including CXL.io (based on PCIe®), CXL.cache, and CXL.mem. These protocols allow both the CPU and devices to share resources and operate on the same memory region for higher performance, reduced data movement, and reduced software stack complexity. By utilizing CXL.io, essentially PCIe 5.0, it retains compatibility with PCIe and enables PCIe features such as link bring-up, enumeration, register access and large block memory transactions.
CXL 2.0 provides support for single-level switches to extend the reach of CXL and enable memory pooling between multiple hosts. By supporting switch-attached memory to enable memory pooling, it allows servers to pool resources – such as accelerators or memory – that can be assigned to different servers, depending on the workload. Memory can be flexibly allocated and deallocated to different servers allowing augmentation from other sources and creating an environment for systems to offer unused local memory to other systems – resulting in better utilization and reduced costs while avoiding overprovision of servers in the rack.
CXL 3.0 introduced fabric connections for scalability, expanded switching to support multi-level switching, added back-invalidate to allow a degree of symmetric coherency, enhanced peer-to-per capabilities, and more. CXL specifications maintain backward compatibility to ensure systems are interoperable and decrease time spent on deployment and OpEx.
CXL Consortium members are taking advantage of the new CXL capabilities and actively developing storage devices that can be byte-addressable. CXL fabrics help datacenters establish disaggregated composable infrastructures while CXL technology addresses bandwidth challenges modern datacenters are facing, allowing individual server design and configuration that meets performance demands. Even volatile memory can be connected via CXL to become part of an overall shared, pooled, and disaggregated solution. With CXL technology, datacenters are advancing their existing architectures and delivering cost-efficient memory solutions across their systems. Join the Consortium’s efforts to advance an interoperable ecosystem for heterogeneous memory and computing solutions, by becoming a member via https://www.computeexpresslink.org/join.