Join us for the upcoming “Compute Express Link™ 2.0 Specification: Memory Pooling” educational webinar airing Tuesday, March 23, 2021, from 9-10 am PT. Last November, the CXL Consortium announced the CXL 2.0 specification which introduces support for switching, memory pooling, and persistent memory – all while preserving industry investments by supporting full backward compatibility with CXL 1.1.
In this webinar, you will:
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Learn how CXL 2.0 supports memory pooling for multiple logical devices (MLD) as well as a single logical device with the help of a CXL switch.
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Understand how the CXL switch enables servers to pool resources such as accelerators and/or memory that can be assigned to different servers depending on the workload.
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Explore the standardized fabric manager for inventory and resource allocation to enable easier adoption and management of CXL-based switch and fabric solutions.
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Immediately following the presentation, we will be hosting a live, interactive Q&A discussion to address attendee questions.
Webinar presenters:
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Mahesh Wagh, CXL Consortium Protocol Working Group Co-Chair and Senior Principal Engineer, Intel Corporation
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Rick Sodke, Associate Technical Fellow, Microchip Technology Inc.
Learn more about the CXL 2.0 specification: