Registration is complimentary for all CXL Consortium Members. Register to attend the event HERE.
Cancellation Policy: Registrations canceled less than 7 days prior to the event will be assessed a $50 cancelation fee to offset facility costs. Please email admin@computeexpresslink.org to cancel your registration.
If you are not currently a member of the CXL Consortium, learn about our membership benefits HERE and contact admin@computeexpresslink.org with any questions or for additional information.
Alonso Cheng is a lead engineer on the PCIe/CXL VIP development team at Siemens, with over 10 years of experience in the EDA industry. He has contributed to the development and delivery of PCIe, CXL, LPIF VIPs and has played a key role in several high priority customer verification projects. In addition, he has supported customers working with other major protocols, including CPI, CXS, and AXI, helping address integration and verification challenges.
Alonso’s expertise spans high speed protocol verification, including PCIe/CXL RC, EP, Switch, and retimer technologies. He is passionate about understanding customer requirements and real world use cases and finds fulfillment in working closely with customers to deliver effective and practical verification solutions.
Avdhesh Chhodavdia, Technologist, Astera Labs
Avdhesh Chhodavdia is a security technologist at Astera Labs, where he drives architecture and security initiatives for next-generation connectivity solutions. With over a decade of experience in platform security, Avdhesh has been instrumental in shaping the design and deployment of advanced data center security technologies. Prior to Astera labs, he worked at Microsoft on Device and Azure silicon security deployments, and at Meta on device security and virtualization in consumer devices to enable privacy. At Astera Labs, he focuses on building secure, scalable architectures that meet the demanding requirements of AI infrastructure and cloud-scale platforms.
Byeonghun Hwang is a Staff Engineer at Samsung Electronics. He joined Samsung in 2021. His work focuses on Retrieval-Augmented Generation (RAG), KV cache management, and optimizing large-scale AI workloads. Recently, he has been exploring the application of CXL-based memory solutions, such as CMM-D, to improve performance and efficiency in AI systems.
With an academic background in Electrical & Computers Engineering, I joined Synopsys in 2015 as a verification engineer for the PCI-Express Controller team. Being part of a dynamic team operating on an ever-evolving product, I have specialized in testbench architecture and performance analysis. Currently, I lead major activities in these two areas for our PCI-Express and CXL Controller.
Geof Findley has over 38 years in the tech industry. He currently is the World Wide Vice President of Business Development and Sales at Montage Technology, Inc. since March 2018. Prior to this role, Geof Findley spent 19 years at Intel Corporation, where positions included Director of Memory Enabling in the Data Center Group, focusing on aligning the memory industry around Intel’s products, and Channel Alliance Manager, emphasizing market timing and partnership optimization. Earlier experience includes roles in engineering, programming, sales, business development and strategic program management at IBM, Siemens, and NICE. Geof Findley holds a Bachelor of Science in System Engineering from the University of Arizona and a Master of Business Administration from Santa Clara/St. Edward’s University
Gordon is Senior Director, Product Management at Teledyne LeCroy. He has been working on PCI Express technologies for 25 years. Gordon is an active contributor to the CXL Compliance Program and has contributed to the test specifications for both PCI Express and CXL. Gordon graduated from Glasgow University with a Bachelor’s degree in Electronics and Music and a MSc in Information Technology from the University of Paisley.
Gustavo is a Functional Validation Engineer at Intel, specializing in CXL interconnect validation for bleeding-edge Xeon SoC products. He focuses on building test content and automation frameworks, applying software engineering best practices to prevent bugs from reaching customers and ensure correctness at the silicon, firmware, OS, and system levels. Gustavo is passionate about AI-driven validation tooling and actively participates in hackathons and challenges spanning hardware validation, data science, and IoT.
Luis Ancajas is Director of CXL Business Development at Micron Technology, where he leads strategy and ecosystem partnerships for next generation memory solutions supporting AI and data center workloads. With a background in computer architecture and semiconductors, he focuses on advancing CXL architectures with hyperscalers and infrastructure partners. Luis holds an M.S. in Electrical Engineering from Stanford University and a B.S. in EECS from UC Berkeley
Nilesh Shah is VP Business Development, ZeroPoint Technologies. Additionally. He participates and contributes regularly at standards bodies like SNIA, OCP, JEDEC, RISC-V, CXL Consortium. He is regularly invited to speak at Conferences, and has led multiple panels and featured in Analyst/ Press interviews, focused on AI and memory technologies. Previously, Nilesh led Strategic Planning at Intel Corporation’s Non Volatile Memory Solutions Group, where he was was responsible for the product planning and launch of the Data Center SSD products and Pathfinding innovations. Nilesh advises several startups in the AI Data Center, memory and GPU space
Sandeep Dattaprasad is a Distinguished Engineer at Astera Labs with 15+ years of experience in semiconductor, software diagnostic tools, developing security strategies and firmware development for complex SoC product lines including Compute Express Link products, SAS RAID controllers, SAS expanders and PCIe switches. He is also a contributing member of the CXL Consortium. At Astera Labs, Sandeep’s focus is on driving product strategy for new market segments by translating data center bottlenecks into profitable and competitive hardware and software solutions.
With 13 years of experience in verification IP engineering, I specialize in advanced protocols including CXL, PCIe, Memory protocols like DFI, HBM,GDDR,DDR etc and AMBA protocols like AXI3,ACE and CHI. My expertise spans architecture definition, testbench development, and debugging complex SoC environments. I have led multiple projects involving protocol compliance, interoperability, and performance validation, collaborating closely with cross-functional teams to deliver robust verification solutions.
Yamini Shastry. Director, Customer Success. Experienced in building and delivering test and analysis solutions for high speed networks. An expert in protocol analysis focusing on compute, storage and transport technologies including Ethernet, FC, SAS, PCIe and CXL. As the leader of the Customer Success team at VIAVI, she drives exceptional client outcomes and technical excellence.
Yongjin Cho is the Chief Product Officer (CPO) at Panmnesia, where he leads initiatives that shape the company’s role in next-generation computing technologies. Prior to Panmnesia, Yongjin Cho has held various job titles including customer engineer, account manager, solutions architect, and research engineer at Moloco, AWS Korea, and Samsung Electronics and he gained extensive full-stack AI/ML experiences from infra to applications.
Yongjin Cho earned his Ph.D. in Electrical and Electronics Engineering from the University of Southern California, where he also completed a Master’s degree in Computer Science. This strong academic foundation, paired with his practical industry experience, has enabled him to make meaningful contributions to the development of CXL technology and other semiconductor innovations. At Panmnesia, Yongjin Cho focuses on strengthening collaboration and refining development practices, guiding his team to create innovative solutions that support the company’s vision of leading AI infrastructure and connectivity technologies.
Zhihong graduated with a Ph.D. in EDA from the University of Massachusetts Amherst. He developed and architected verification IPs for more than 20 years since joined in Avery design systems. He is now a software engineering director in Siemens EDA and continues to serve as verification architect for PCIe, CXL, NVMe and other IO protocols.
Zongyao Wen is a Sr. Director of R&D at Synopsys. Wen has worked on Verification IP for 28 years. Wen owns CXL VIP product and previously led the development of AMBA, InfiniBand, USB 3/4, PCIe products and VIP technologies. Wen also worked on hardware security verification studies.
SPONSORSHIP OPPORTUNITIES
Please contact admin@computeexpresslink.org with any questions regarding sponsorship.
Exhibitor Sponsorship (6 available) – $5,000
| Lanyard Sponsor (SOLD OUT) – $2,000
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Networking Hour Sponsor (1 available) – $6,000
| Parking Sponsor (1 available) – $3,000
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Daytime Food & Beverage Sponsor (1 available) – $5,000
| Water Bottle Sponsor (SOLD OUT) – $2,500
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Collateral Only Sponsor (Unlimited) – $500
| Branded Sponsorship (Unlimited) – $250
|
LOCATION
CXL Mini DevCon 2026 will be held at the Santa Clara Marriott located at 2700 Mission College Blvd, Santa Clara, CA 95054.
LODGING
A room block at the Santa Clara Marriott is being held for any interested attendees.
Lodging rate: $259/night
Book your room at the CXL Mini DevCon 2026 group rate HERE. Opportunity expires July 10!
PARKING
Parking is available onsite at the Santa Clara Marriott at a discounted rate for all attendees.
Parking Rate: $15/day
TRANSPORTATION
This hotel does not offer shuttle service.
Transportation to location:
Bus Station: San Jose Diridon Station
Subway Station:
Train Station: Santa Clara Great America Station