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CXL DevCon 2024

Apr 30 - May 1, 2024
Santa Clara, California

CXL Consortium Developers Conference (DevCon) 2024
April 30 – May 1, 2024
Santa Clara, California

The CXL Consortium is looking forward to hosting the first Compute Express Link® (CXL®) DevCon from April 30 – May 1, 2024, in Santa Clara, California!

CXL DevCon is a unique opportunity for our Members to learn directly from CXL technology experts. Attendees will participate in CXL technical training, view available products and technology demonstrations, and network with industry peers.

Register for the event HERE.

If you are not currently a member of the CXL Consortium, learn about our membership benefits HERE and contact admin@computeexpresslink.org with any questions or for additional information.

Thank you to our Sponsors!

CONFERENCE PROGRAM

DevCon 2024 Day 1 – Compliance & Implementation
Time Title Presenter(s)
8:00 – 9:00 Registration
9:00 – 9:15 Welcome Jim Pappas, Intel – CXL Chairman
9:15 – 9:45 Keynote – History of CXL Larrie Carr, Rambus – CXL President
9:45 – 10:15 CXL Specifications Overview Debendra Das Sharma, Intel – TTF Co-Chair
10:15 – 10:45 Coffee Break & Exhibit
10:45 – 11:30 Technical Spec Training (1.0/2.0) Mahesh Wagh, AMD – TTF Co-Chair
11:30 – 12:00 CXL Use Case – CXL Native Memory Bill Gervasi, Wolley
12:00 – 1:00 Lunch & Exhibit
1:00 – 1:20 Proving CXL scale-out and ROI in the data center Ira Weiny, Linux
1:20 – 1:40 CXL Software Ecosystem: The Software Stack for CXL Steve Scargall, MemVerge
1:40 – 2:00 Exploring Sunfish™: An Open-source Composable Disaggregated Infrastructure Framework Michael Aguilar, OpenFabrics Alliance – OFA Secretary
2:00 – 2:20 RAS for Resilient Data Centric Platforms using a CXL Memory Controller Sandeep Dattaprasad, Astera Labs
2:20 – 2:40 Member Implementation: CXL Memory Latency Measurement Tutorial Tam Do, Microchip
2:40 – 3:10 Break & Exhibit
3:10 – 3:30 Understanding the Need for Compliance Anil Godbole, Intel
3:30 – 3:50 Testing CXL links using Exercisers & Analyzers Yamini Shastry, Viavi
3:50 – 4:10 CXL Testing – Protocol Layers & Testing Examples Gordon Getty, Teledyne LeCroy
4:10 – 4:40 Focusing on the Future of CXL Compliance Nathan White, Intel – CWG Co-Chair
4:40 – 5:00 Day 1 Open Q&A CWG / TTF Panel
5:00 – 6:30 Networking Reception & Exhibit

 

DevCon 2024 Day 2 – Emerging & Future
Time Title Presenter(s)
8:00 – 8:30 Registration and Exhibit
8:30 – 9:30 Technical Spec Training (3.0/3.1) Rob Blankenship, Intel – PWG Co-Chair
9:30 – 10:00 Member Implementation: Streamlining CXL Adoption for Hyperscale Efficiency Nilesh Shah, ZeroPoint Technologies
10:00 – 10:30 Technical Training – Security: Integrity and Data Encryption (IDE) Trends and Verification Challenges in CXL Zongyao Wen, Synopsys
10:30 – 11:00 Coffee Break & Exhibit
11:00 – 11:20 Member Implementation: Empowering Memory Expansion and Sharing to Modern Applications with CXL 3.1 Dr. Miryeong Kwon, Panmnesia
11:20 – 11:40 Member Implementation: CXL 2.0 Use Case – Using Both DDR4 & DDR5 on the Same Server to Allow Memory & Bandwidth Scaling Geof Findley, Montage Technology
11:40 – 12:10 Member Implementation: Using a CXL 2.0 switch for CXL memory expansion, pooling and sharing Jianping (JP) Jiang, PhD, Xconn Technologies
12:10 – 12:30 Member Implementation Lou Ternullo, Rambus
12:30 – 1:30 Lunch & Exhibit
1:30 – 1:50 Member Implementation: Improving system memory bandwidth with CXL software interweaving Ravi Kiran Gummaluri, Micron
1:50 – 2:10 Member Implementation: Exploring system memory expansion and memory pooling/tiering Kapil Sethi, Samsung
2:10 -2:30 Member Implementation: Enabling CXL Memory Module, Exploring Memory Expansion Use Cases & Beyond Thomas Won Ha Choi, PhD, SK hynix
2:30 – 2:50 Member Implementation: Optical Applications of CXL David Kulansky, Alphawave Semi
2:50 – 3:30 Break & Exhibit
3:30 – 4:30 Fireside chat – open discussion + audience Q&A Leadership Panel
4:30 – 5:00 Closing comments and Call to Action Kurtis Bowman, AMD – MWG Co-Chair

SPEAKERS

David Kulansky, Alphawave Semi

Dave Kulansky is Director of Product Marketing at Alphawave Semi focused on High-Speed IO. Dave has 20+ years of semiconductor experience, focused on mastering best fit solutions to streamline new product development. Before joining Alphawave, Dave held positions in AMS, RF & SerDes design, but he most recently focused on PCIe & Ethernet solutions.

Dave holds degrees from Princeton University & Johns Hopkins University.

Kurtis Bowman, AMD

Kurtis Bowman is the Marketing Working Group Co-Chair of the CXL Consortium and Director, Server System Performance at AMD. With more than 25 years of experience in the architecture, development, and business justification of server, storage, commercial, and consumer computing products, his current areas of interest include converged and hyperconverged systems, heterogeneous compute elements for HPC & machine learning, and data analytics. He has built teams and managed firmware and hardware development through entire lifecycles in both startups and mature companies. Mr. Bowman earned a BSEE from New Mexico State University, holds multiple patents, and has written articles in the technical and trade press.

Mahesh Wagh, AMD

Mahesh Wagh is AMD Sr. Fellow, Server System Architect in the AMD Datacenter System Architecture and Engineering team, developing world-class products and solutions around EPYC processors. Prior to joining AMD, Mahesh was a Senior Principal Engineer at Intel corporation, focusing on IO and SoC architecture and related technology developments. He has broad experience in chipset and IO architecture, design and validation on both Server and Client platforms. Some of Mahesh´s significant achievements include the enhancements to PCI Express Architecture and Specification, leading CPU IO domain architecture and IO IP architecture & Interfaces and leading AMD´s Compute Express Link (CXL) efforts.

Sandeep Dattaprasad, Astera Labs

Sandeep Dattaprasad is a Senior Product Manager at Astera Labs with 15+ years of experience in semiconductor, software diagnostic tools, developing security strategies and firmware development for complex SoC product lines including Compute Express Link products, SAS RAID controllers, SAS expanders and PCIe switches. He is also a contributing member of the CXL Consortium. At Astera Labs, Sandeep’s focus is on driving product strategy for new market segments by translating data center bottlenecks into profitable and competitive hardware and software solutions using CXL technology.

Anil Godbole, Intel

Anil is a Senior Marketing Manager for Intel’s Xeon Product Planning and Marketing Group. His domain is in Memory, Serdes Technologies & Associate Protocols (DDRx, CXL, PCIe, Ethernet, etc..).
Previously, he was a Design Engineer in CPU-support ASICs, FPGAs.

Jim Pappas, Intel

Jim Pappas is the Director of Technology Initiatives at Intel Corporation. In this role, Jim is responsible to establish broad industry ecosystems that comply with new technologies in the areas of Enterprise I/O, Energy Efficient Computing, Solid State Storage, and Persistent Memory. Jim has founded, or served on several organizations in these areas including: PCI Special Interest Group, Universal Serial Bus (USB), Storage Networking Industry Association (SNIA), InfiniBand Trade Association (IBTA), Open Fabrics Alliance (OFA), The Green Grid (TGG), Compute Express Link (CXL), and many others. Jim has over 30 years of experience in the computer industry. He has been granted eight U.S. patents in the areas of computer graphics and microprocessor technologies. He has spoken at dozens of major industry events and holds a B.S.E.E. from the University of Massachusetts, Amherst, Massachusetts.

Debendra Das Sharma, Intel

Debendra Das Sharma (Senior Member, IEEE) was born in Odisha, India, in 1967. He received the B.Tech. degree (Hons.) in computer science and engineering from IIT Kharagpur, Kharagpur, India, in 1989, and the Ph.D. degree in computer systems engineering from the University of Massachusetts, Amherst, MA, USA, in 1995.,He joined Hewlett-Packard, Roseville, CA, USA, in 1994, and Intel, Santa Clara, CA, USA, in 2001. He is currently an Senior Fellow with Intel. He is responsible for delivering Intel-wide critical interconnect technologies in Peripheral Component Interconnect Express (PCI Express), Compute Express Link (CXL), Universal Chiplet Interconnect Express (UCIe), Coherency Interconnect, Multi-Chip Package Interconnect, and Rack Scale Architecture. He has been leading the development of PCI-Express, CXL, and UCIe inside Intel as well as across the industry since their inception. He holds 160+ U.S. patents and more than 400 patents worldwide.,Dr. Das Sharma has been awarded the Distinguished Alumnus Award by IIT, in 2019, the 2021 IEEE Region 6 Engineer of the Year Award, the PCI-SIG Lifetime Contribution Award in 2022, and the 2022 IEEE CAS Industrial Pioneer Award. He is currently the Chair of UCIe Board, a Director of PCI-SIG Board, and the Chair of the CXL Board

Ira Weiny, Intel

Ira Weiny is a maintainer of the CXL Linux stack and is currently developing the Dynamic Capacity Device (DCD) support for the Linux kernel.

Ira has been a Linux kernel contributor for more than 15 years. He has a background in large HPC clusters and was involved in the initial CXL Linux development.

Steve Scargall, MemVerge

As a Senior Product Manager and Software Architect at MemVerge, Steve Scargall stands at the forefront in the field of memory technology, where he pioneers the development of cutting-edge software-defined memory solutions leveraging Compute Express Link (CXL) devices. With a rich kernel development, file system development, and performance analysis background, Steve possesses a unique blend of technical acumen and visionary leadership. His work seamlessly connects the dots between theoretical innovation and practical utility in-memory technology, setting new benchmarks for excellence in the industry. Steve’s expertise drives the advancement of MemVerge’s product offerings and shapes the future direction of memory technology applications.

Tam Do, Microchip Technology Inc.

Tam Do is a member of the technical product marketing team within the Data Center Solutions business unit at Microchip with more than 20 years of experience in the semiconductor industry.
Before joining Microchip, Tam started his career in circuit design in mixed signal systems, and have worked on video codec and high-speed interface products in the consumer and multimedia markets. Since 2012, he transitioned to technical product marketing. Currently Tam is responsible for Microchip PCIe/CXL products.

He has a Bachelor of Science in Electrical Engineering from the University of Nevada-Reno and an MBA from the University of Phoenix.

Ravi Kiran Gummaluri, Micron Technology, Inc.

Ravi Kiran Gummaluri is the Director for CXL system Architecture, CXL Solutions Group, at Micron Technology, developing world-class products and solutions around CXL Memory Modules. Prior to joining Micron, Ravi led the CCIX and CXL solutions in Xilinx. He has vast experience in providing end-to-end solutions around coherent interconnects. With a rich kernel development and performance analysis background and with good understanding of end-to-end solutions, Ravi possesses a unique blend of technical acumen and visionary leadership. His work seamlessly connects the dots between theoretical innovation and practical system level solutions, setting new benchmarks for excellence in the industry. He has a master’s degree in Embedded Systems Design. He has deliver

Geof Findley, Montage Technology

Geof Findley is an award-winning presenter, patent holder and systems engineer with a proven track record of successfully managing multiple aspects of engineering, sales and marketing to ensure successful product launches and ramps. With over three decades of experience, Geof has developed unmatched depth and breadth of expertise across product development, sales, marketing, and channel management.

Geof spent over 19 years at Intel Corporation, where he held various roles, including Director of Memory Enabling: Platform Memory Operations, Data Center Group from 2003 to 2018. Prior to Intel, Geof worked in sales and engineering roles in telecommunications for Siemens/ROLM, Altitude Software, and NICE systems. Since March 2018, Geof has served as the World Wide Vice President of Business Development/Sales at Montage Technology, Inc. where he has increased sales 4X and brought on two new product lines in Retimers and CXL along with their award winning memory products.

Geof is known for his drive to collaborate with individuals and teams to identify and solve issues. He maintains a large, global network of influencers and decision-makers, contributing to his success in driving business development and sales initiatives.

Michael Aguilar, OpenFabrics Alliance

Michael Aguilar is a Senior Computer Scientist for HPC Research and Development at Sandia National Laboratories, working with both Capacity Computing and Advanced Architecture Testbeds. Michael is responsible for management of Sandia’s ARM64 HPC systems, including Astra, and is active with the OpenFabrics Alliance, as the Board Secretary. He is currently serving as Co-Chair of the OpenFabrics Management Framework (OFMF) Working Group. In addition, Michael is involved in Sandia Labs BeeGFS research and development. Michael has a Masters of Science degree in Computer Science and a Bachelor of Science in Computer Engineering.

Dr. Miryeong Kwon, Panmnesia

Dr. Miryeong Kwon holds the position of Chief Strategy Officer and is a founding partner at Panmnesia, Inc. Her work is pivotal in the development of a robust CXL ecosystem, offering detailed solutions across both hardware and software aspects of CXL technology. At the helm of Panmnesia’s next-generation development campus, Dr. Kwon oversees a dedicated team. This team is engaged in exploring advanced CXL intellectual properties, focusing on CPU root-ports, switches, and a variety of endpoints, alongside establishing a CXL test and validation framework.

Prior to her tenure at Panmnesia, Dr. Kwon was distinguished with a Ph.D. degree from the Korea Advanced Institute of Science and Technology (KAIST), where she was honored with the Outstanding PhD Dissertation Award. This accolade is reserved for the most exemplary doctoral thesis among all academic disciplines at KAIST. In addition to her academic achievements, she was invited as a guest researcher at the Lawrence Berkeley National Laboratory.

Dr. Kwon’s scholarly contributions include authoring 40 research papers that have significantly advanced the fields of computer architecture and operating systems through the integration of CXL cache coherent interconnect technologies. Furthermore, her innovations have led to the acquisition of 14 technical patents, each contributing to the foundational elements of CXL technology.

Larrie Carr, Rambus

Larrie Carr is the VP of Engineering at the newly formed Interconnect SoC business unit at Rambus Inc. He is leading the development and architecture of Rambus’ new product initiatives which are focused on enabling memory connectivity, expansion, pooling, and switching using CXL technology. Before Rambus, Larrie was a Technical Fellow at Microchip Technology responsible for technical strategy and architectural guidance for Microchip’s broad portfolio of datacenter solutions, including serial memory controllers, SSD controllers, RAID solutions, PCIe switches, SAS expanders, and other initiatives not publicly announced. While at Microsemi Corporation (later acquired by Microchip), Larrie led internal innovation and external technical engagements related to OpenCAPI, Gen-Z, Compute Express Link (CXL) and RISC-V within the Microsemi CTO organization. Among other outcomes, these engagements resulted in the development and eventual productization of the industry’s first in-production serial memory controller ASIC (OMI to DDR4). Prior to Microsemi, Larrie led product architecture for PMC-Sierra’s enterprise storage business unit from inception to an industry leadership position. During that tenure he established PMC-Sierra as a technology leader in the area of storage connectivity, security, reliability, availability, and serviceability – concepts that extend well into the tiered memory architecture that the CXL standard will enable. He also served as a private consultant conceiving many of the industry’s first-generation non-volatile memory solutions. He earned a bachelor’s degree and master’s degree in electronic engineering from Simon Fraser University in Vancouver, Canada.

Kapil Sethi, Samsung

Kapil is currently Director in the New Business Planning team at Samsung Semiconductor where he leads product planning for Samsung’s CXL® technology based products. He has been at Samsung Semiconductor for 3 years. Previously, Kapil has worked as Product Manager leading multi-million dollar product lines.

Thomas Won Ha Choi, SK hynix

Thomas Won Ha Choi is a Distinguished Engineer and Memory Systems Architect at SK hynix, specializing in memory standardization and pathfinding. Thomas is involved in various memory standardization projects in CXL Consortium and JEDEC, and he is experienced with standardization of emerging memory interfaces related with DRAM and persistent memory. His standardization and pathfinding experiences are very wide, from the development of next-generation DRAM specifications such as DDR5 and the post-DDR5 interface, to next-generation memory interconnect including CXL, CCIX, Gen-Z, and JEDEC NVDIMM-P. Furthermore, Thomas is experienced with system-level performance analysis, and memory performance simulation methodologies that can be utilized for specification works of future memory technologies.

Thomas is a co-chair of DRAM Sub-group within the CXL Consortium Technical Working Groups, contributing to specification works related to DRAM features that were integrated into CXL3.1 Specification. His CXL presentations include 1) co-presenting a CXL Consortium webinar in June 2021 with the topic of Supporting Persistent Memory, 2) presenting SK hynix CXL memory plan in 2022 OCP Global Summit Expo Hall Talk, and 3) presenting CXL memory development works in CXL Forum at 2022 OCP Global Summit. As a significant contributor to memory standardization works, Thomas served as a Director on the Gen-Z Consortium Board of Directors from 2016 to 2022, and was awarded from JEDEC several times including 2020 JEDEC Technical Recognition Award for his contributions to DDR5 and NVDIMM-P, the 2022 JEDEC Outstanding Leadership Award for his outstanding service to JC42.3, and the 2023 JEDEC Chairman’s Award in recognition of JC42 committee contributions.

Thomas has a B.S. degree in Computer Sciences from the University of Texas at Austin, a M.S. degree in Computer Engineering from the University of Southern California, and a Ph.D. degree in Computer Engineering from North Carolina State University.

Zongyao Wen, Synopsys

Zongyao Wen is a Senior Director, product owner of CXL VIP, at Synopsys. Wen has worked on Verification IP for 25+ years. Wen owns CXL VIP product and led the development of AMBA, InfiniteBand, USB 3/4 and PCIe products and VIP technologies. Wen also worked on hardware security verification studies.

Gordon Getty, Teledyne LeCroy

Gordon is Technical Marketing Manager at Teledyne LeCroy. He has been working on PCI Express technologies for 22 years. Gordon is an active contributor to the PCI Express Test Specifications. Gordon graduated from Glasgow University with a Bachelor’s degree in Electronics and Music and a MSc in Information Technology from the University of Paisley.

Yamini Shastry, VIAVI

Yamini Shastry, Director Customer Success is responsible for ensuring VIAVI customers are fully supported on the operation and application of VIAVI Xgig protocol analysis systems. She has 20+ years of software engineering experience with expertise in building and delivering test and analysis solutions for high-speed protocols.

Bill Gervasi, Wolley

Mr. Gervasi is a Principal Systems Architect, Wolley, Inc. He has over 45 years of experience in high speed memory subsystem definition, design, and product development. Career highlights include 19 years at Intel where he was systems hardware designer, software designer, and strategic accounts manager. Mr. Gervasi became a memory specialist for companies including S3, Transmeta, Netlist, SimpleTech, and Nantero, and is now Principal Systems Architect for Wolley, developing CXL based memory solutions.

Mr. Gervasi been involved in the definition of Double Data Rate SDRAM since its earliest inception. He has served on the JEDEC Board of Directors and chaired committees for DRAM parametrics and memory modules during the development of DDR1 through DDR6. He is currently the chairman of the JEDEC Alternative Memory committee. He received the JEDEC Technical Excellence award, their highest honor, in 2020.

Jianping (JP) Jiang, Xconn Technologies

Jianping (JP) Jiang is the VP of Product Marketing and Business Operation at Xconn Technologies, a silicon valley startup pioneering CXL switch IC. At Xconn, he is in charge of CXL ecosystem partner relationship, CXL product marketing, business development, corporate strategy and operations. Before joining Xconn, JP held various leadership positions at several large scale semiconductor companies, focusing on product planning/roadmaps, product marketing and business development. In these roles, he developed competitive and differentiated product strategies, leading to successful product lines that generate over billions of dollars revenue annually. JP has a Ph.D degree in computer science from the Ohio State University.

Nilesh Shah, ZeroPoint Technologies

Nilesh Shah currently leads Business Development at ZeroPoint Technologies where he is responsible for engaging Hyperscalers, Memory Module , controller and processor/accelerator manufacturers to develop Data Center and Smart Device solutions . He’s an active member of the CXL Consortium, JEDEC, SNIA, and represents the company at OCP. Previously, Nilesh developed Data Center SSD products and Computational Storage initiatives at Intel and holds several patents in this area. Nilesh runs several Meet Up Communities with upwards of 5000 active members and serves as an Advisor to companies in the Emerging Memory Technology IP and SoC space