The CXL Consortium is looking forward to presenting at the STAC Summit – New York event to highlight the benefits of CXL for trading and analytics.
- Presentation title: Memory Is the New Bottleneck, And It’s Now Software Defined
- Date and time: May 20 at 9:35 am ET
- Speaker:Oren Benisty, VP Business Development, UnifabriX
- Abstract: Compute performance in modern AI, ML, and cloud workloads is no longer constrained primarily by cores or accelerators, but by memory capacity, bandwidth, and fragmentation. Conventional server-centric memory architectures statically bind DRAM to individual hosts, resulting in stranded capacity, NUMA imbalance, overprovisioning, and poor elasticity as model sizes and in-memory datasets continue to grow.
This talk presents a technical deep dive into how Compute Express Link (CXL) fundamentally changes memory system design by decoupling memory from compute and enabling fabric-attached, composable memory architectures. We examine CXL devices, memory pooling models, and CXL fabric topologies, including switched fabrics and emerging multi-host environments. Special attention is given to the Dynamic Capacity Device (DCD) model and its implications for runtime memory expansion, contraction, and isolation.
We explore how dynamic memory provisioning can be implemented using CXL fabric managers, memory region management, and operating-system integration, highlighting the control plane mechanisms required to allocate, resize, and reclaim memory without rebooting or workload interruption. Architectural tradeoffs around latency domains, fault containment, and scalability are discussed in the context of production deployment.
To ground the discussion, we reference a real-world implementation of software-defined memory built on CXL switching as a case study. This example illustrates how CXL fabric management, dynamic allocation policies, and runtime orchestration can be combined to reduce memory fragmentation and overprovisioning in large AI clusters. The focus remains on the architectural principles and engineering decisions required to make dynamic CXL memory practical at scale, rather than on any specific product.
Register for the event HERE.