CXL Consortium representatives will be providing an update from the Consortium and highlighting the benefits of CXL technology for AI and HPC applications during the following session:
Exhibitor Forum presentation: CXL Consortium Progress Report: Available CXL Devices in the Market
- Date and time: Tuesday, November 19, 10:30 – 11:00 am ET
- Speakers: Kurtis Bowman (AMD) and Anil Godbole (Intel)
- Location: B206
- Description: CXL Consortium member companies are developing CXL solutions capable of enabling HPC and AI workloads with increased system scalability and flexibility. To support the ecosystem of CXL devices entering the market and ensure interoperability in the industry, the CXL Consortium has advanced its compliance program by hosting Compliance Test Events and establishing the CXL Integrators List featuring our member’s CXL solutions. This session will begin with an update from the Consortium and discuss the growth of the CXL Compliance program, as well as the ecosystem of CXL devices including IP, operating platforms, storage, system-level products, and more. The session will also highlight CXL solutions showcased in the CXL Pavilion (booth #1807) and the necessary components to deploy CXL technology.
Birds of a Feather presentation: Using CXL to improve performance of AI language models
- Date and time: Tuesday, November 19, 12:15 – 1:15 pm ET
- Speakers: Kurtis Bowman (AMD), Rita Gupta (AMD), Anil Godbole (Intel), and Larrie Carr (Rambus)
- Location: B204
- Description: Increased demand for AI applications highlights the “memory wall” obstacle – a capacity and bandwidth memory transfer bottleneck. CXL facilitates memory sharing between accelerators and GPUs while enabling direct-attached memory (i.e. DRAM) to any node, improving memory bandwidth, performance, and capacity for AI language models.This session will explore the advantages of memory sharing and DRAM improvements for CPU, GPU, and CPU plus GPU-based memory applications utilizing AI language models, such as RAG and LlaMA. Attendees will learn about performance, cost, and power consumption benefits of DRAM and CXL memory modules.
Visit the CXL Pavilion in booth #1807 to view the following CXL technology demonstrations.
- Alphawave Semi / Amphenol: 64 Gbps CXL® 3.1 Subsystem IP (PHY + Low Latency Controller) Supporting OSFP-XD Direct Attach Cabling
This demo will showcase Alphawave Semi’s 64 GT/s CXL 3.x Subsystem with Amphenol’s internal and external cabling solutions enabling the industry to make the move to disaggregated server resources within a data center rack as well as several rack-to-rack use cases. Alphawave Semi’s CXL 3.x subsystem solution is supporting Amphenol’s first-to-market OSFP-XD PCIe Direct Attach Cables and delivering a reach of at least 4m AND/OR CopprLink™ internal MCIO + CEM Connector + M.2 channel demonstrating internal and external I/O connectivity solutions. For more information, visit https://awavesemi.com/silicon-ip/phy-ip/pcie-phy-ip/.
- AMD: Boosting Workload Scalability: CXL® Memory Tiering powered by AMD EPYC for AI and Beyond
Memory-intensive applications, such as in-memory databases, graph processing engines, and AI/ML frameworks, are becoming increasingly prevalent in today’s datacenters. Traditional server systems often face the “memory wall” — a bottleneck in memory capacity and bandwidth. CXL expands both the memory capacity and bandwidth of a system, which is essential for enhancing the performance of modern applications. At Supercomputing 2024, AMD will showcase the advantages of a CXL-enabled system powered by AMD EPYC CPUs, demonstrating how modern large language models, AI/ML frameworks, and in-memory applications can achieve significant performance gains on a CXL-enabled tiered memory system.
- Astera Labs: Accelerating AI and HPC Workloads with Leo CXL® Smart Memory Controllers
Astera Labs and partners will demonstrate how CXL-attached memory benefits applications such as AI and HPC. We’ll show how our Leo Smart Memory Controller can deliver high-bandwidth and capacity CXL memory to optimize AI workloads. We will also demo enhanced diagnostics and telemetry for fleet management and reliable deployment of CXL at cloud-scale.
- Cadence: CXL® 3.1 System Demo with Protocol Analysis
Cadence will show CXL 3.1 Root Complex Demo board and CXL 3.1 Endpoint Demo board in back to back configuration. Showcasing CXL 3.1 traffic. Protocol Analyzer may be used to show traffic. For more information, visit www.cadence.com/en_US/home/tools/silicon-solutions/protocol-ip/pcie-and-compute-express-link.html.
- Intel: Enable CXL® Memory with Intel® Xeon® 6 CPUs
This demo will showcase the query rate on a RAG database running on a server augmented with CXL memory.
- MemVerge: AI Use Cases for Server CXL® Memory Expansion and Shared CXL® Memory
MemVerge will show a suite of AI use cases for CXL Server Expansion and Shared Memoryincluding, an LLM RAG pipeline using server expansion, Stable Diffusion using CXL shared memory, Global Shared Memory Objects (GISMO) in collaboration with Micron, plus Dynamic Capacity Device and Hotness Tracking in partnership with SK hynix.
- Microchip Technology Inc.: SMC 2×00 – CXL® 2.0 DDR4/5 Smart Memory Controllers
This demo will show direct attached CXL memory performance benchmarks. For more information visit www.microchip.com/en-us/products/memory/smart-memory-controllers.
- Micron Technology: Memory sharing made possible with CZ122 Memory Expansion and Fabric Attached Memory File System (FAM-FS)
Demonstrating RocksDB benchmark running on CXL fabric attached shared memory orchestration using Micron’s CZ122 CXL Memory Modules.- Hardware Platform: 14 Micron CZ122 devices enumerated with XConn switch and multiple Intel Xeon5 based CXL servers
- Software: Micron’s fabric attached memory file system. Open source Linux contribution.
- Application: RocksDB
For more information, visit www.micron.com/cxl and https://github.com/cxl-micron-reskit.
- Panmnesia: HPC Applications on Panmnesia’s CXL 3.1 Server Including the Full Hardware/Software Stack
Our CXL 3.1 Server contains CXL-CPUs, CXL Switches, and CXL Memory Expanders. We will show the execution of practical HPC/Data Center(DC) applications such as atomic-level simulation and large-scale AI service on our CXL 3.1 Server. Through this demo, we will show how the CXL 3.X features such as Direct P2P and memory sharing can accelerate real-world applications. For more information, visit www.youtube.com/watch?v=TEC3xMAtBy8.
- Phison: Optimizing CXL Connectivity for Faster, Low-Latency Data Transfer and Superior Signal Integrity
Phison PS7201 retimer is a 16-lane, low-power, low-latency, symmetrical PCIe Gen5, and CXL 2.0 integrated retimer. For more information, visit www.phison.com/en/retimer-ic.
- Synopsys / Teledyne: Synopsys CXL® 3.x PHY + Controller IP with the Teledyne LeCroy Summit M616 Protocol Exerciser
A complete hardware demo of CXL 3.0 with an end-to-end system from root complex to endpoint using all Synopsys IP. The demo showcases real PCIe 6.x / CXL 3.x technology available today that is already being widely deployed by many companies. It features Systems and IP that are already on the PCI-SIG 5.0 Integrators List and have been taken to the first 6.0 Pre-FYI Compliance workshops, including the only PCIe 6.0 Host system that runs the CV.
- Teledyne LeCroy: Industry’s First CXL® Test and Validation Solution
There are 2 parts to our demo, one part is our CXL 2.0 Test appliance, the second is Protocol Analyzer/Exerciser with Compliance testing- The OakGate CD280-G5 is a CXL 2.0 validation platform is used to test the interoperability, performance, functionality, security and power behavior of CXL 1.1 and 2.0 memory devices at scale (up to 8 DUTS). For more information, visit www.teledynelecroy.com/protocolanalyzer/summit-m616-analyzer.
- The Summit M616 Protocol Analyzer and Exerciser is used for Validation, Verification, Error Injection and Compliance Testing. For more information, visit www.teledynelecroy.com/protocolanalyzer/summit-m616-analyzer.
- UnifabriX Memory Pool: Revolutionizing System Performance for AI and HPC
Join us for an exciting demonstration by UnifabriX, showcasing a production-level CXL Memory Pool system featuring multiple hosts and Dynamic Memory Allocation (DCD). This event will highlight the capabilities of our Fabric Manager, Memory Pool, Host Agents, and the execution of HPC workloads. Witness firsthand how these features are applied in real HPC/AI environments. Don’t miss this opportunity to see cutting-edge technology in action! For more information, visit www.UnifabriX.com.
- VIAVI: CXL® 2.0 over Optics with VIAVI PCIe Platform and Rambus Controller via Samtec Interconnect
This demo will show a CXL link over PCIe using VIAVI’s Exerciser at the root complex with the Rambus DUT, as the end point. Additional information is available here: https://computeexpresslink.org/blog/rambus-viavi-and-samtec-demonstrate-cxl-over-optics-poc-at-upcoming-sc24-3171/.
- Xconn Technologies: Scalable Memory Pooling/Sharing with CXL® 2.0
We will show a CXL memory pooling and sharing system, composed of CXL 2.0 server CPUs, CXL 2.0 switch, CXL 2.0 FM (Fabric Manager), and CXL 2.0 memory devices. For more information, visit www.xconn-tech.com.
- ZeroPoint Technologies: Hyperscale Dynamic Compressed Memory Tier
FPGA prototype of a Dynamically adjusting Composable Memory Tiered system, with in-line memory compression.Hyperscalers like Google and Meta have issued their minimum requirements to make CXL deployments commercially viable at Hyperscale via the OCP Hyperscale CXL Tiered Memory Expander Specification.We will demonstrate a portable IP solution that can be dropped into any CXL Memory Controller Device to immediately comply with and exceed the Hyperscaler requirements, and accelerate the deployment of CXL powered systems at scale. The demo will showcase a fully functional IP Solution, with dynamically adjusting compressed memory tier and Memory Capacity Expansion capability running representative Data Center Hyperscaler workloads on top of Linux’s memory tiering stack.