The CXL Consortium is excited to participate in the upcoming Supercomputing 2023 (SC’23) event in Denver, CO. CXL technology experts and Consortium member companies will demonstrate the evolution of the CXL specification, highlight use cases and the expansion of the CXL device ecosystem. View the comprehensive list of Consortium activities below:
CXL Presentations
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Birds of a Feather: Increasing Memory Utilization and Reducing Total Memory Cost Using CXL
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Date and time: Tuesday, November 14, 2023, 12:15 – 1:15 pm MT
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Location: Rooms 405, 406, and 407
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Moderator: Kurtis Bowman and Kurt Lender, CXL Consortium MWG Co-Chairs
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Panelists: Tracy Spitler (IntelliProp), Vijay Nain (Micron), Bill Gervasi (Wolley)
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Join our panel of experts to discover how CXL’s advanced memory expansion and fabric management capabilities can increase system scalability and flexibility to enable resource sharing for higher performance, reduced software stack complexity, and lower datacenter memory cost.
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Exhibitor Forum: Compute Express Link (CXL): Advancing Coherent Connectivity
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Date and time: Thursday, November 16, 2023, 2:00 pm MT
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Location: Rooms 503 and 504
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Speaker: Kurt Lender, CXL MWG Co-Chair
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Receive the latest update from the CXL Consortium and learn more about enhancements included in the latest release of the CXL specification. Plus, find out more about the CXL technology demos available in the Consortium booth (#1301)
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CXL Technology Demonstrations
The CXL Consortium will host live CXL technology demos at the CXL pavilion (Booth #1301) from the following member companies:
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AMD: Enhancing AI with CXL Memory Tiering
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Astera Labs: Demonstrating Breakthrough Memory Bandwidth and Performance for HPC and AI with Leo Memory Connectivity Platform
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Cadence: Silicon-Proven Subsystem IP for CXL Host and Endpoint from Cadence Live Demo with Viavi Protocol Analyzer
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Intel: CXL Memory Modes on Future Generation Intel Xeon CPUs
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IntelliProp: Composable and Managed CXL Fabric Demo
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Lightelligence: Photowave: Optical CXL Interconnect for Composable Data Center Architectures
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Microchip: HP Memory Capacity & Bandwidth Expansion
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Micron: Micron CZ120 Memory Capacity Expansion for AI & HPC Workloads Using CXL
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Rambus: CXL Tiered Memory Platform Development Kit for Performant Memory Scaling
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Samsung: Graph DB Application on CXL Memory Enabled System
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Siemens EDA: CXL Performance Optimization & Validation SW Development Kit
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Synopsys / Teledyne LeCroy: CXL 2.0 Interop and Compliance Testing with Teledyne LeCroy Summit Z516 Protocol Exerciser
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UniFabrix: MAXimize HPC and AI Speed with: MAX® memory and Storage Machine
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Viavi: CXL 2.0 Exerciser and Analyzer System
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Xconn Technologies: CXL 2.0 Memory Pooling (Sharing) Using Xconn Switch
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ZeroPoint Technologies: Hardware Accelerated CXL Memory Compression
We hope to see you at the CXL pavilion to explore the benefits of CXL technology for HPC industry and learn directly from technical experts behind the technology’s development. View the event agenda for more information and follow the CXL Consortium on Twitter and LinkedIn for updates during the event.
Contact press@computeexpresslink.org to schedule a meeting with CXL Consortium representatives and learn more about the technology.