REGISTRATION RATES
- Adopter Members – $500
- Contributor and Promoter Members – $300
Register HERE to reserve your seat!
REFUND POLICY
- Adopter Member Regular Rate registration fee – $35.38
- Contributor/Promoter Regular Rate registration fee – $21.96
Keynote Presenter
Objective Analysis / Jim Handy
Jim has over 35 years in the electronics industry including 20 years as a leading semiconductor and SSD industry analyst. Early in his career he held marketing and design positions at leading semiconductor suppliers including Intel, National Semiconductor, and Infineon. A frequent presenter at trade shows, Mr. Handy is highly respected for his technical depth, accurate forecasts, widespread industry presence and volume of publication. He has written hundreds of market reports, articles for trade journals, and white papers, and is frequently interviewed and quoted in the electronics trade press and other media. He posts blogs at www.TheMemoryGuy.com, and www.TheSSDguy.com.
Altera
Divya Vijayaraghavan is a Technical Leader at Altera in San Jose. She has worn many hats in her career ranging from being a vertical champion and subject matter expert for UPI and CXL customer enablement and proliferation to a technical lead for FPGA acceleration solutions and technical manager for several key customers and ecosystem partners. She has 26 granted patents and has represented Altera on industry standards committees such as the PCI-SIG.
AMD
Kurtis Bowman is Marketing Working Group Co-Chair of the CXL Consortium and Director, Server System Performance at AMD. With more than 25 years of experience in the architecture, development, and business justification of server, storage, commercial, and consumer computing products, his current areas of interest include converged and hyperconverged systems, heterogeneous compute elements for HPC & machine learning, and data analytics. He has built teams and managed firmware and hardware development through entire lifecycles in both startups and mature companies. Mr. Bowman earned a BSEE from New Mexico State University, holds multiple patents, and has written articles in both the technical and trade press.
Astera Labs
Chris Petersen is a Fellow of Technology and Ecosystems and is responsible for pathfinding for the Astera Labs’ product roadmap and driving the ecosystem enablement for all new products. Chris has more than 20 years of in-depth experience in architecting AI and cloud servers, memory, storage, accelerators, fabrics, and datacenter solutions. Prior to Astera Labs, Chris led the technology and infrastructure roadmap at Meta for 11 years. He also serves on the Board of Directors for the UALink Consortium.
Sandeep Dattaprasad is a Senior Product Manager at Astera Labs with 15+ years of experience in semiconductor, software diagnostic tools, developing security strategies and firmware development for complex SoC product lines including Compute Express Link products, SAS RAID controllers, SAS expanders and PCIe switches. He is also a contributing member of the CXL Consortium. At Astera Labs, Sandeep’s focus is on driving product strategy for new market segments by translating data center bottlenecks into profitable and competitive hardware and software solutions using CXL technology.
Cadence
Nishant Jain is part of the PCIe/CXL controller IP team working out of the Noida, India Office. He Joined Cadence in 2024 and has ~12 years of industry experience. Currently leading the CXL Design in Cadence Design System and overall architecture and microarchitecture of CXL and the related interfaces. Previously, he has worked on cutting edge IP’s for Radar and Vision processing for MIPICSI2 subsystems, High-Speed Aggregator for XR/VR/AR chips, PCIe SS for the Accelerators, DSI Subsystems for the premium tier segments, Debug interfaces for Measurements, DSP subsystems for the Gasoline/Electric Motor Control Systems. Nishant holds eight US Patents in Image Processing and other fields.
Tejbal Prasad is part of the PCIe/CXL controller IP team working out of the Noida, India Office. He Joined Cadence in 2018 and has ~18 years of experience working on various VLSI industry protocols. Tejbal currently leads the verification team for CXL in Cadence Design System. Previously, he worked on cutting edge IP’s for Radar and Vision processing including Signal Processing Toolbox & ISP. He led a verification team of ~10 engineers and was responsible for overall verification starting from Architecture exploration discussion to Verification Env architecture buildup through creation/execution of test and closure of verification activities. He holds four US Patents in Radar/Image Processing and other fields.
Shu Wang is a Senior Software Engineering Manager at Cadence Design Systems, leading the CXL Verification IP design and verification team. Having more than nine years of experience in Verification IP development, Shu specializes in CXL and PCIe VIP testing, protocol compliance, and interoperability validation and has also contributed to USB3.0/USB3.1/USB3.2 and GDDR6 Memory Model VIP development.
Intel
Tony Benavides is a Memory Systems Architect with more than 25 years of industry experience, specializing in Compute Express Link (CXL) technologies for Intel’s Xeon products. He chairs the JEDEC CXL Memory Controller Technical Group, leading the development of future CXL memory controller specifications. As Co-chair of the CXL Consortium Technical Task Force, Tony collaborates with industry leaders to bring the latest CXL specifications to market.
Sai Srikar Chalagalla is a Platform Hardware Design Engineer within the Data Center and AI (DCAI) Group at Intel Corporation. He is responsible for validating the Reliability, Accessibility, and Serviceability (RAS) implementation of IIO and Memory features (i.e., PCIe, CXL, DDR) in Intel Xeon Platforms. He has been with Intel Corporation for 2+ years and holds a M.S. degree in Computer Engineering from Arizona State University.
Anil Godbole is a CXL Marketing Working Group Co-Chair and Senior Marketing Manager for Intel’s Xeon Product Planning and Marketing Group. His domain is in Memory, Serdes Technologies & Associate Protocols (DDRx, CXL, PCIe, Ethernet, etc.). Previously, he held a position as Design Engineer in CPU-support ASICs, FPGAs.
Shubhada Pugaonkar is a Platform RAS Architect specializing in RAS software and firmware solutions in the Data Center and AI group at Intel. With 18+ years of experience in the industry, she is responsible for Platform RAS architecture on Xeon Server Platforms and holds an M.S. in Computer Engineering.
Jackrabbit Labs
Grant Mackey is the CTO of Jackrabbit Labs, a memory fabrics company, whose mission is to enable the next generation of data centers through software. An avid supporter, consumer, and contributor of open source software, Grant was a pioneer for voluntary open source efforts while employed at Western Digital. He is an industry veteran familiar with data center, storage, and memory fabric architectures, and has advanced these areas through simulation, prototype, and productization efforts throughout his career.
Microsoft Azure
Daniel Berger is a Principal Researcher at Microsoft Azure Research. His work focuses on improving the efficiency, sustainability, and reliability of cloud platforms. After five years of working on CXL, Daniel is particularly excited about building real systems – from prototypes to production. Before joining Microsoft, Daniel taught distributed systems and datacenter classes at Carnegie Mellon University. He is the recipient of an ACM ASPLOS 2023 distinguished paper award, USENIX OSDI 2023 best paper award, 2021 ACM SOSP Best Paper Award, and best paper awards at IFIP Performance and ACM WiSec.
Montage Technology
Geof Findley has held the role of Vice President of Business Development and Sales at Montage Technology, Inc. since March 2018. Previously, he spent 17 years at Intel Corporation in positions including Director of Memory Enabling in the Data Center Group, focusing on aligning products with JEDEC standards, and Channel Alliance Manager, emphasizing market timing and partnership optimization. His earlier experience includes roles in business development and strategic program management at Intel Corporation and 11 years as a Senior Sales Representative at Royal Trading – Unify. Geof holds a B.S. in System Engineering from the University of Arizona and a MBA from St. Edward’s University.
Panmnesia
Yongjin Cho is a business development lead at Panmnesia. Prior to Panmnesia, Yongjin has held various job titles including customer engineer, account manager, solutions architect, and research engineer at Moloco, AWS Korea, and Samsung Electronics and he gained extensive full-stack AI/ML experiences from infra to applications. He holds a PhD in computer engineering and is a member of the marketing workgroups of both CXL Consortium and UALink Consortium.
Rambus
Lou Ternullo is Sr. Director Product Marketing for the Rambus CXL/PCIe controller IP product lines. He has more than 30 years of experience in the semiconductor industry in memory design and engineering management and 15+ years of experience in product management/marketing and business development in IP and ASIC related businesses. Lou’s experience in technology and product related disciplines include memory and high speed memory and storage interface IP as well as CXL and PCIe interface IP. He has leveraged his experience in the IP and ASIC businesses to drive product definition and execution of complete products that enable customer success and has held leadership positions at Virage logic, Cadence and eSilicon. He holds a MBA from Lehigh University and MS in Electrical Engineering from Rochester Institute of Technology.
Samsung
Jinin So is a Senior Director & System Architect at Samsung, responsible for developing advanced CXL products and technologies, including CMM-DC (Computing), CMM-B (Disaggregated Memory System), and SMDK (Software Stack for CXL Products). He has played a key role as lead architect in developing multiple groundbreaking technologies, such as the world’s first CXL Process Near Memory Platform (CMM-DC), CXL Memory Expander (CMM-D), and DDR-based Near Memory Process DIMM (AXDIMM) at Samsung. Jinin has a deep knowledge of computer architecture, particularly in CPU/GPU/NPU with memory subsystems, and in-depth expertise in Intel/AMD server systems and memory configurations for high-performance servers. With more than 10 years of experience in memory module design, system-level SI/PI/thermal analysis, and five years in Process Near Memory System Architecture design, Jinin has contributed to defining memory module product specifications within JEDEC. He holds more than 10 U.S. patents and has authored more than 10 publications.
ScaleFlux
Tong Zhang is currently a Professor in the Electrical, Computer and Systems Engineering Department at Rensselaer Polytechnic Institute (RPI), NY. In 2002, he received a PhD. in electrical engineering from the University of Minnesota. He has graduated 20 PhD students and published more than 170 research papers with an h-index of 44. In 2014, he co-founded ScaleFlux and currently serves as its Chief Scientist. His current and past research spans computer systems, VLSI signal processing, and error correction coding and he is a Fellow of the IEEE.
Siemens
Heetashi Arora is a Lead Member of Consulting Staff for CXL VIP Development at Siemens, with more than 11 years of experience in the EDA industry. She has extensive expertise in CXL and PCIe generations, as well as a background of simulation-to-emulation VIP development. Prior to her work in VIP development, Heetashi focused on emulation solutions and its performance aspects. She holds a BS in Electronics and Communication.
Wade Chen holds a master’s degree in communication engineering from National Taiwan University and specializes in PCIe/CXL IC Design Verification. As the senior verification engineer and project leader of the Siemens Avery CXL VIP Team, he brings five years of experience in PCIe/CXL VIP development and support. Wade’s main responsibilities include scheduling feature roadmaps aligned with CXL Specification updates, providing high-quality support to IC Design customers, developing the CXL Compliance test suite, and managing team members.
SK hynix
Jungmin Choi is a Director and Memory System Architect in Memory Systems Research at SK hynix. He is responsible for developing the memory system architecture for CXL-based memory solution. He joined SK hynix in 2018, working on system-level architecture design for emerging memory solutions and has a diverse background spanning memory devices to controllers with expertise in the areas of CPU, GPU, DSP, FPGAs, fabric interconnect, and memory systems.
Santosh Kumar is currently Director at SK Hynix America DRAM Technical Planning, in charge of next generation memory solutions like CXL & Processing-in-Memory. During his more than 10 years with SK hynix America, he has held various technical and planning leadership roles in NAND and SSD storage groups. Previously, Santosh was Principal Engineering Technologist at Dell and was responsible for leading SSD, NVM technologies, storage media card strategy, and advanced engineering evaluation. He has more than 25 years’ experience in architecture and management roles leading global engineering teams in the SOC system and storage industries. Santosh holds a Master Degree in Electronic Instrumentation from the NIT Warangal, India, and has 10+ patents in the fields of storage and data security.
SmartDV Technologies
Ettore Antonino Giliberti is an electronic engineer specializing in embedded systems, with several years of experience in SoC architecture, hardware/software co-design, and development; including hands-on work on FPGA and RISC-V-based platforms. In his current role as Senior Staff Application Engineer at SmartDV Technologies, Ettore collaborates and supports customers in achieving success for their projects with SmartDV Design and Verification IPs.
Synopsys
Umabaskari Kaliyanasundaram has 18+ years of professional experience in the field of ASIC/SOC Design Verification. She completed a BS in Electrical Engineering and a MS in VLSI System design and has been working with Synopsys Inc since 2016 as functional verification expert of ASIC Digital IPs for UFS & CXL Protocols using UVM Verification Methodology. Uma established, mentored and managed CXL Logic RTL Design and Verification Teams at Synopsys India Pvt Ltd. and is currently working on the functional verification of CXL 3.0/UCIe Protocols using UVM Verification Methodology at Synopsys Inc, USA.
VIAVI
Yamini Shastry is Director, Customer Success at VIAVI. Experienced in building and delivering test and analysis solutions for high speed networks, she is an expert in protocol analysis focusing on compute, storage and transport technologies including Ethernet, FC, SAS, PCIe and CXL. As leader of the Customer Success team at VIAVI, she drives exceptional client outcomes and technical excellence.
Viking Technology
Brian Stark is currently a Principal Engineer with Viking Technology, and holds a B.S. in Mathematics and a Master’s Degree in Computer Science. He has more than 35 years of experience in computational engineering and began his career developing firmware, device drivers, and APIs for devices and analyzers using high-speed bus protocols for both military and commercial applications. He has supported device development in the memory and storage markets and is an expert in manufacturing support, encompassing R&D, device bring-up, verification/validation, and production test support. He has experience developing products from the concept stage through the entire life cycle and his notable achievements include the successful development of the firmware, software stack, and BIOS support for Viking’s NVDIMM product line and serving as the Design Validation Test Director for DRAM and Flash-based designs. He previously developed solutions for cabled PCIe expansion and prototyping of a platform interconnect using Non-Transparent Bridging. Brian’s extensive knowledge of PCIe and DDR memory modules gives him a unique insight into the potential of CXL.
Xconn Technologies
Jianping (JP) Jiang is the Senior VP of Product Marketing and Business Operation at Xconn Technologies, a silicon valley startup pioneering CXL switch IC. At Xconn, he is in charge of CXL ecosystem partner relations, CXL product marketing, business development, corporate strategy and operations. Before joining Xconn, JP held various leadership positions at several large-scale semiconductor companies, focusing on product planning/roadmaps, product marketing and business development. In these roles, he developed competitive and differentiated product strategies, leading to successful product lines that generate billions in revenue annually. JP has a PhD in computer science from Ohio State University.
Visit with members and view practical demonstrations of CXL Technology in our expanded Exhibit Hall!
2025 Exhibit Hall Hours
Day 1 – April 29
- 8:00 – 9:00 AM
- 10:30 – 11:00 AM
- 12:30 – 1:40 PM
- 3:00 – 3:30 PM
- 5:00 – 6:30 PM
Day 2 – April 30
- 8:00 – 9:00 AM
- 10:30 – 11:00 AM
- 12:20 – 1:30 PM
- 3:00 – 3:30 PM
2025 Exhibitors
2025 Sponsors
LOCATION
CXL DevCon 2025 will be held at the Santa Clara Marriott located at 2700 Mission College Blvd, Santa Clara, CA 95054.
LODGING
A room block at the Santa Clara Marriott is being held for any interested attendees.
Lodging rate: $299/night
Book your room at the CXL DevCon 2025 group rate HERE. Opportunity expires April 13!
PARKING
Parking is available onsite at the Santa Clara Marriott at a discounted rate for all CXL DevCon 2025 attendees.
Parking Rate: $15/day
TRANSPORTATION
This hotel does not offer shuttle service.
Transportation to location:
Bus Station: San Jose Diridon Station
Subway Station:
Train Station: Santa Clara Great America Station