Rambus: CXL Tiered Memory Platform Development Kit for Performant Memory Scaling
This demonstration will preview the high degree of flexibility and configurability offered by the Rambus CXL platform development kit (PDK). Benchmarking software will be running in a production server demonstrating the effective use of memory tiering through the Rambus CXL PDK. Audience members will be encouraged to customize and update the PDK’s behavior using in-box […]
Micron: Micron CZ120 Memory Capacity Expansion for AI & HPC Workloads Using CXL
Our Live Demo shows with CXL not only we can increase memory capacity of > 1 TB per CPU, we also showcase performance improvement as we are seeing improved in bandwidth of 18-22%. Learn more by visiting www.micron.com/cxl.
Microchip: HP Memory Capacity & Bandwidth Expansion
The SMC2000, CXL Smart Memory Controller, facilitates HPC applications by increasing the memory capacity available per core and memory bandwidth per core.
IntelliProp: Composable and Managed CXL Fabric Demo
IntelliProp’s CXL Extensible Memory Modules enables the composable data center transformation – fundamentally changing the performance, efficiency, and cost of data centers. Learn more by visiting https://intellipropipcores.com/.
Cadence: Silicon-Proven Subsystem IP for CXL Host and Endpoint from Cadence Live Demo with Viavi Protocol Analyzer
Astera Labs: Demonstrating Breakthrough Memory Bandwidth and Performance for HPC and AI with Leo Memory Connectivity Platform
Astera Labs is demonstrating its Leo Smart Memory Controllers, the industry’s highest performant memory controller, enabling CXL-attached memory for memory-intensive AI and HPC workloads. Learn more: Leo Smart Memory Controllers Cloud-Scale Interop Lab for CXL Video: Leo Breaks Through the Memory Wall Video: Accelerating Database Performance with Leo
AMD: Enhancing AI with CXL Memory Tiering
ZeroPoint Technologies: Hardware Accelerated CXL Memory Compression
ZeroPoint Technologies will demonstrate an integrated, Hardware Accelerated Compression Engine, seamlessly adding a new Compressed CXL Memory tier to the system Memory Hierarchy.Background: Hyperscaler end customers like Meta and Google employ software data compression today in production to tier memory into 3 level hierarchy: DRAM, software Compressed DRAM and SSD. They spend up to 5% […]
Viavi: CXL 2.0 Exerciser and Analyzer System
VIAVI CXL protocol test solutions provide tools necessary to debug, analyze and perform validation of CXL links on an integrated exerciser and analyzer platform. To learn more visit: VIAVI CXL test solutions.
Synopsys / Teledyne LeCroy: CXL 2.0 Interop and Compliance Testing with Teledyne LeCroy Summit Z516 Protocol Exerciser
Teledyne LeCroy and Synopsys are showcasing at SC’23 protocol analysis and compliance testing of CXL based devices through a demo interop using Synopsys CXL 2.0 complete solution and the Teledyne LeCroy Summit Z516 Protocol Exerciser. Learn more about the Teledyne LeCroy CXL Protocol Analyzers and Exercisers here. Learn more about Synopsys CXL IP complete solution with controller, […]