Compute Express Link™ (CXL™) 2.0 ECN: Significant Improvements in device management, RAS, Security and more!

CEDT CFMWS & QTG DSM: This ECN is an optional feature that enables the OS to natively assign addresses to Type-3 memory devices. The ECN also introduces a new Device Specific Method (_DSM) to enable the OS to select the optimum QoS Throttling Group (QTG) for a given device range without having to understand the host implementation aspects and policies regarding the QTG assignment.

Add Mailbox Ready Time: This ECN extends mailbox capabilities to add a device advertised mailbox interface ready time and provides a timeout value for device drivers to wait for the mailbox interface to be ready after a reset.

Add Vendor Specific Extension to Register Locator DVSEC: This is an optional feature that allows vendors to use a CXL specified mechanism to provide a pointer to vendor specific register blocks.

Error Isolation on CXL.mem and CXL.cache: PCIe® and CXL.io support Downstream Port Containment (DPC), which is intended to halt all traffic below a Downstream Port after an unmasked uncorrectable error is detected at or below the Port to avoid the potential spread of data corruption. This ECN offers the same capability on the CXL.cache and CXL.mem protocols to enhance reliability on the CXL Link. It defines a formal transaction timeout mechanism for Host initiated transactions on CXL.mem and CXL.cache. It defines capability, control, and status registers to isolate uncorrectable errors for error containment on CXL.mem and CXL.cache at the CXL Root Port.

Memory Device Error Injection: This ECN introduces an additional optional compliance DOE (Data Object Exchange) interface to inject a class of errors that are specific to Type-3 devices. This will allow vendors to design vendor specific mechanisms to inject errors, using a common compliance interface.

NULL CXL Capability ID: This ECN defines a NULL CXL Capability IDthat is used to identify the group of registers in the CXL.cache and CXL.mem register block in the CXL Component Register space. This will simplify the hardware design if one or more CXL capabilities need to be made unavailable based on theconfiguration or the SKU.

Compliance Tests for Viral Error Injection: Viral error indication is an additional error containment mechanism. This ECN defines additional compliance tests to address interoperability verification for Viral error reporting.

Component State Dump Log: This ECN defines a new Component State Dump Log for reading state dump information for a component that allows state dump information to be extracted using a specification defined mechanism to enable an industry standard host tool to collect this information. The ECN also introduces the concept of Clear Log, Populate Log, and Get Log Capabilities.

Compliance DOE Return Value: Compliance DOE provides a “request” to query the support DOE Capabilities. This ECN enables compliance software to query the support compliance capabilities of the device.

Compliance DOE 1B: An enhancement to the existing test algorithm (referred to as 1B) to simplify the implementation and use of Test Algorithm 1B by re-assigning the “Inject Bogus Writes” DOE Request (Request Code 5) to “Multiple Write Streaming with Bogus Writes”.

QoS Telemetry Compliance Testcases: Originally, QoS Telemetry was not included in the CXL 2.0 Compliance Chapter. This ECN shares testcases proposed for basic testing of QoS Telemetry controls to ensure interoperability and basic functionality as well as FM API and SLD Control and Status command sets.

CXL.cachemem IDE Establishment Flow: This ECN defines the CXL.cache/mem Key Programming protocol and how it may be utilized to establish the CXL.cache/mem IDE stream in an interoperable manner.

Devices Operation in CXL 1.1 mode with no RCRB: The CXL 2.0 specification requires CXL 2.0 devices to interoperate in CXL 1.1 mode when connected to a CXL 1.1 host. A CXL 2.0 device needs to morph the register map dynamically based on the outcome of training (CXL 2.0 vs. CXL 1.1). This ECN enables an additional design option that eliminates the need for the morphing of the register map and thus simplifies the design of CXL 2.0 devices while still enabling compatibility with the CXL 1.1 host.

3, 6, 12 and 16-way Memory Interleaving: This ECN defines the changes needed to Type-3 devices that are needed to enable additional interleaving options and permit interleave sets that are made up of 3, 6, 12 or 16 devices. It also adds support for XOR based memory interleave calculation to CEDT that some hosts support.