During the latest CXL Consortium webinar, Mahesh Natu (Intel Corporation) presented an overview of the CXL 3.X specification and how it provides support for AI and ML workloads for cloud and on-premise applications. Attendees also learned how CXL 3.2 builds upon these advancements for CXL memory devices, optimizing device management, functionality, and security.
Watch On-Demand or Download the Slides
If you were not able to attend the live webinar, the recording is available via YouTube and BrightTALK and the webinar presentation slides are available for download on the CXL Consortium website.
| Webinar on YouTube | Webinar on BrightTALK | Download Slides |
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Webinar Q&A
We received great questions from the audience but were not able to address them all during the webinar. Below, we’ve included answers to the questions we didn’t get to during the live webinar.
Q: How can I tell the difference between a CXL 3.2 device, a CXL 3.1 device and a CXL 3.0 device?
If you look at the CXL specification, there is no registration that says, “I’m a 3.2 device” or “I’m a 3.1 device” and so on, and that’s on purpose. There is no such thing as a CXL 3.2 device. When folks say a CXL 3.0 device, they typically mean a device that operates at PCI Gen 6 bandwidth and speed. There is no way to differentiate between them because the software can make use of each of the features without knowing which spec version the device vendor was reading when the device was implemented.
Q: Is TSP compatible with other confidential computing technologies like TDISP?
With technologies like TDISP, which is a PCI Express defined technology that allows similar TSP tested VMs to make use of PCI devices, TSP was defined on top of similar concepts and constructs compared to TDISP. In the CXL protocol, TSP has to do some additional work to meet the security requirements. Within the CXL Consortium, numerous CPU vendors are developing CXL devices for various applications, like quantum computing. Each of these devices would be compatible with other technologies like TDISP.
Q: What are the benefits of OS-based SW tiering over application-based tiering?
When the system has different memory classes, one that’s highly performant and one that’s not quite as performant for example, there are different ways to optimize the usage of the page. You want to make sure your hot pages or frequently accessed pages are in the higher performance memory, which can be done at the OS level or application level. Generally, the OS-level approach is better because it’s done once and benefits all of the applications. You don’t need to recompile your applications with this approach. It scales better in terms of enabling ecosystem usage. Our goal is to improve OS-based technologies. We want to make sure that the standard interface that CHMU defines allows a pure OS-based memory tiering solution.
Related Links on the CXL Consortium Website