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Past CXL Specifications Landing Page

CXL 3.0 Specification Archive

CXL 3.0 Specification

CXL 3.0 Errata and Clarifications to the Compute Express Link Consortium Specification | August 2022

CXL 3.0 Errata and Clarifications to the Compute Express Link Consortium Specification | December 2023

CXL 2.0 Specification Archive

CXL 2.0 Specification

CXL 2.0 Errata and Clarifications to the Compute Express Link Consortium Specification | May 2021

CXL 2.0 Engineering Change Notice: CEDT CFMWS & QTG DSM | May 2021

CXL 2.0 Engineering Change Notice: Error Isolation on CXL.mem and CXL.cache | July 2021

CXL 2.0 Engineering Change Notice: Add Mailbox Ready Time | July 2021

CXL 2.0 Engineering Change Notice: Compliance ECN – Memory Device Error Injection | July 2021

CXL 2.0 Engineering Change Notice: Add Vendor Specific Extension to Register Locator DVSEC | July 2021

CXL 2.0 Engineering Change Notice: NULL CXL Capability ID | July 2021

CXL 2.0 Engineering Change Notice: Compliance Tests for Viral Test Injection | September 2021

CXL 2.0 Engineering Change Notice: Component State Dump Log | September 2021

CXL 2.0 Engineering Change Notice: QoS Telemetry Compliance Testcases | September 2021

CXL 2.0 Engineering Change Notice: Compliance DOE 1B | September 2021

CXL 2.0 Engineering Change Notice: Compliance DOE Return Value | September 2021

CXL 2.0 Engineering Change Notice: Type 3 Management Using MCTP CCI | November 2021 

CXL 1.1 Specification Archive

CXL 1.1 Specification

CXL 1.1 Errata and Clarifications to the Compute Express Link Consortium Specification | November 2019

CXL 1.1 Errata and Clarifications to the Compute Express Link Consortium Specification | February 2020

CXL 1.0 Specification Archive

CXL 1.0 Specification